The present invention is directed to a switch for use with ATM Utopia bus master and slave devices and finds particular application in implementations where multiple bus masters share connections with multiple bus slaves.
Asynchronous transfer mode (ATM) is a communication protocol which uses fixed length cells (packets) to transfer information between communication units. Typically, such cells are communicated between master and slave device across so-called Utopia busses, a well known bus standard. Such Utopia busses are commonly found in ATM communication units such as ATM switches and the like.
An example of an ATM switch is shown in FIG. 4, ATM switch 10 includes a number of line cards (1-M) 12, each of which have a number of ATM interfaces 14. The ATM interfaces 14 may be any communication medium adapted for carrying ATM cells, such as optical fiber communication links, wireless communication links or traditional wired communication links. Line cards 12 provide a variety of functions including connections/terminations for data interfaces and/or voice interfaces.
Line cards 12 are interconnected with one another across a backplane 16 through a switch core 18. Backplane 16 may be any of a variety of electrical interconnects including an ATM backplane or a backplane based on other communication protocols such as the well-known peripheral computer interconnect (PCI) communication bus. Switch core 18 operates to provide interconnection among the various line cards 12. Switch core 18 may be based upon a variety of technologies depending upon the manufacturer.
As indicated above, the line cards 12 may provide a variety of termination points for inbound ATM traffic from ATM interfaces 14. Not all of this traffic, however, will share common termination points. For example, voice information carried in ATM cells typically is terminated at one or more digital signal processors (DSPs). It is the function of the DSPs to reassemble time division multiplexed voice traffic from the plurality of ATM cells. Data traffic, on the other hand, often terminates at a ATM segmentation and reassembly (SAR) engine or other communication controller (e.g., a virtual network interface or other communication controller). Although these different traffic types have different termination points, traditional line card implementations generally route all inbound traffic from the ATM interfaces through a common bus structure. This presents a problem in that additional processor overhead is needed when routing voice traffic verses data traffic. Accordingly, it would desirable to have a means at the line card level to allow for segregation of inbound traffic.
A communication bus snooper switch includes an inbound cell queue coupled to receive ATM cells from a number of ATM physical layer interfaces across a common inbound bus. An out-bound cell queue (which may be the same queue as the inbound cell queue when a dual port queue is used) is coupled to provide the ATM cells to separate ATM termination points according to cell address information across separate out-bound busses. Each of the out-bound busses is associated with one of the ATM termination points. The snooper switch is configured to operate as an ATM bus master when communicating with the physical layer interfaces and as an ATM bus slave when communicating with the ATM termination points. During transmit operations, cells from the various ATM termination points are queued in corresponding transmission cell queues within the snooper switch and, thereafter, are provided to the ATM physical layer interfaces according to an arbitration scheme implemented at the snooper switch.
In one embodiment the switch includes an inbound cell queue coupled to receive ATM cells from a number of ATM physical layer interfaces across a common inbound bus. An out-bound cell queue is coupled to provide the ATM cells to separate ATM termination points according to cell address information across separate out-bound busses. Each of the out-bound busses is associated with one of the ATM termination points. The switch is also configured to operate as an ATM bus master when communicating with the physical layer interfaces and as an ATM bus slave when communicating with the ATM termination points. The physical layer interfaces may be any appropriate interfaces such as ADSL modems and/or native ATM interfaces. The inbound and out-bound cell queues, which are found in the receive path, may be implemented as a single dual port queue using, for example, a dual port memory device.
The switch may further have an arbitrator configured to select the appropriate location within the inbound cell queue for a received ATM cell according to the physical layer interface from which the received ATM cell originates. In addition, one or more look-up tables may be provided, the look-up tables being configured to indicate which of the ATM termination points is to receive a cell stored in the inbound cell queue. In some cases, these look-up tables may be implemented as content addressable memories coupled to the inbound cell queue.
In addition, the switch may include a number of cell availability registers, each being associated with a respective one of the ATM termination points and being coupled to a respective one of the content addressable memories. And, in addition to a receive path, the switch may include a transmit path having a number of transmission cell queues, each corresponding to a respective one of the ATM termination points and being coupled to such corresponding respective ATM termination point. A multiplexer may then be used to couple the transmission cell queues to a common out-bound transmission bus coupled to the physical layer interfaces.
In a further embodiment, a communication interface (e.g., an ATM communication interface) is provided. The communication interface includes a first number of physical layer interfaces configured to act as bus slaves when transmitting and/or receiving communication units across a shared communication bus. The interface further includes a second number of communication termination points each configured to act as communication bus master when transmitting or receiving communication units across dedicated communication busses. Further, the interface includes a switch coupled between the physical layer interfaces and the communication termination points. The switch is configured to act as a communication bus master when exchanging communication units with the physical layer interfaces and as a communication bus slave when exchanging communication units with the communication termination points. In some cases, the communication units may be ATM cells, however, in general any packetized form of information may be used.
In some cases, the switch which is part of the communication interface may include a receive queue which is coupled to receive ATM cells or other communication units from the physical layer interfaces across the shared communication bus. The switch may further have a number of transmit queues each configured to receive communication units from respective ones of the communication termination points across a corresponding one of the dedicated communication busses. Preferably, but not necessarily, the receive queue and the transmit queues are all dual port queues.
The switch may be configured to notify one of the communication termination points when a cell for that communication termination point has been received into the receive queue. Such notification may be accomplished by setting a bit in a cell availability register corresponding to the respective termination point. Such a bit may be set in the cell availability register in response to the output of a look-up table, which may be implemented as a content addressable memory coupled to the receive queue.
These and other features of the present invention will be apparent from the detailed description and its accompanying drawings.